Speaker
Description
The Phase-2 upgrade of the CMS experiment will involve the replacement of many detector components, preparing the experiment for operation at the HL-LHC. During this upgrade, the silicon tracker detector will be completely replaced. The development of the prototypes and the quality assurance testing on the mass-produced final version of the new tracker sensor modules requires a flexible electronic testing infrastructure, capable of interfacing the modules with a computer. This infrastructure is based on the FC7, an AMC card equipped with a Xilinx Kintex-7 FPGA and jointly designed by CERN and Imperial College, running the uDTC gateware. A key component of uDTC is the Command Processor Block, responsible for the real-time configuration and operation of the modules during testing. In this technical presentation we present the development process and the final implementation of the new Command Processor Block for the uDTC, focusing on architecture choices and lessons learned from this development.
